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mirror of synced 2025-09-23 12:18:44 +00:00

change precedence rules to follow python

This commit is contained in:
schaeff 2020-07-09 16:10:01 +02:00
parent 4290b991f0
commit 23365529aa
2 changed files with 7 additions and 5 deletions

View file

@ -11,6 +11,8 @@ def main(field g) -> (field):
field e = if 2 >= 1 && 4 > 5 || 1 == 1 then 1 else 0 fi
field f = if 1 < 2 && false || 4 < 5 && 2 >= 1 then 1 else 0 fi
0x00 ^ 0x00 == 0x00
//check if all statements have evalutated to true
a * b * c * d * e * f == 1
return g

View file

@ -36,15 +36,15 @@ mod ast {
PrecClimber::new(vec![
Operator::new(Rule::op_or, Assoc::Left),
Operator::new(Rule::op_and, Assoc::Left),
Operator::new(Rule::op_bit_or, Assoc::Left),
Operator::new(Rule::op_bit_xor, Assoc::Left),
Operator::new(Rule::op_bit_and, Assoc::Left),
Operator::new(Rule::op_equal, Assoc::Left)
| Operator::new(Rule::op_not_equal, Assoc::Left),
Operator::new(Rule::op_lte, Assoc::Left)
| Operator::new(Rule::op_not_equal, Assoc::Left)
| Operator::new(Rule::op_lte, Assoc::Left)
| Operator::new(Rule::op_gte, Assoc::Left)
| Operator::new(Rule::op_lt, Assoc::Left)
| Operator::new(Rule::op_gt, Assoc::Left),
Operator::new(Rule::op_bit_or, Assoc::Left),
Operator::new(Rule::op_bit_xor, Assoc::Left),
Operator::new(Rule::op_bit_and, Assoc::Left),
Operator::new(Rule::op_right_shift, Assoc::Left)
| Operator::new(Rule::op_left_shift, Assoc::Left),
Operator::new(Rule::op_add, Assoc::Left) | Operator::new(Rule::op_sub, Assoc::Left),